The present invention relates generally to the field of data processing systems, and more particularly to history buffers in a central processing unit.
Central processing units (CPUs) may implement multi-threaded core technologies that involve one or more execution lanes. Each execution lane utilizes a register file (RF) and history buffer (HB) that contains architected register data. Instructions are tagged by the order in which they were fetched. Once the instructions are fetched and tagged, the instructions are then executed to generate results, which also are tagged. The RF may contain results from the most recently executed instructions (i.e., newer register data) and the HB may contain results from previously executed instructions (i.e., older register data). Furthermore, the older register data is displaced by newer register data from one or more entries in the RF to one or more entries of the HB. In some instances, a limited number of entries in the HB may reach a memory capacity and impact CPU performance. Furthermore, the HB and RF are implemented by CPUs to manage architected register data, complete register data, restore register data, and recover register data.